The Fin Field Effect Transistor (Fin FET) is a technology newly emerged in recent years, which makes semiconductor devices have smaller scale and higher performance
FIGS. 1(a) to 1(c) are the three-dimensional schematic drawing, the top view and the sectional view along line BB′ of the Fin Field Effect Transistor in the prior art, respectively. As shown in the figures, the fin 106 made of a semiconductor material is located on the insulating layer 102; the fin 106 comprises a middle portion for forming a channel and end portions for forming source/drain regions 110b and source/drain extension regions 110a; a gate stack covers the middle portion of the fin 106 and extends along a direction vertical to the fin 106, wherein, the gate stack comprises a gate dielectric layer 200, a gate 202 and a hard mask 204; spacers 206 surround the sidewalls of the gate stack and are located above the source/drain extension regions 110a; there is a contact layer 108 on the upper surface of the source/drain regions 110b so as to reduce the contact resistance of the source/drain regions 110b and to improve the performance of the Fin Field Effect Transistor.
In order to suppress short channel effect, the source/drain extension regions needs to be formed with a smaller thickness. In the prior art, the source/drain extension regions are usually formed on both sides of the gate stack by means of ion implantation. There are the following problems when the source/drain extension regions are formed by ion implantation:
1) after performing the ion implantation, the source/drain extension regions need to be annealed to activate the doping ions in the source/drain extension regions, but the annealing can only activate a certain number of doping ions, so there is limitation to the electric conductivity of the source/drain extension regions; and2) since the source/drain extension regions have a smaller thickness, during ion implantation, such aspects as the energy and angle of ion implantation need to be controlled, so the process is complicated and not easily controllable.
Therefore, how to further reduce the contact resistance of the source/drain extension regions in the Fin Field Effect Transistor and meanwhile control the junction depth of the source/drain extension regions by a simple process becomes a burning question.